Solar cells, also known as photovoltaic cells, for converting light into electricity are becoming an increasingly viable source of power when compared to traditional petroleum based sources of energy. Solar cells come in many types including monocrystalline, polycrystalline, and thin-film. Some of the most efficient solar cells, e.g., monocrystalline cells, are thin slices called wafers that are cut from a single silicon crystal produced in the form of an ingot. The silicon may be doped with select impurities to form two separate semiconductor structures, i.e., n-type and p-type semiconductors, used to capture the energy of those photons absorbed by the wafer. A grid of metal may be applied to or otherwise incorporated in the wafer to provide electrical contacts. Groups of cells may then be mounted together and electrically coupled to form a solar panel.
Illustrated in FIG. 1 is a plan view of a photovoltaic silicon wafer 100 including a silicon portion 102 and two separate semiconductor members arranged to support an electric field between associated conductive elements and electrical contacts. The wafer 100 is adapted to directly transform sunlight into electrical energy using a p-n junction incorporated into the side of the wafer opposite the solar exposure. The p-n junction is comprised of p-type and n-type semiconductors applied to or incorporated into the wafer 100 by doping the wafer with boron and phosphorous atoms, respectively. The p-type semiconductor is coupled to and schematically represented by a first edge bar 110 and a first plurality of cross bars spanning the wafer 100 or a region thereof. The first plurality of cross bars includes one or more intermediate cross bars 112 and two cross bars 114 at the outer side edges of the wafer 100. The n-type semiconductor is coupled to and schematically represented by a second edge bar 120 and a second set of cross bars 122 that are parallel to and interdigitated with the first plurality of p-type cross bars 112, 114 to create a sequentially alternating pattern of p-type and n-type semiconductors and associated conductive elements. The first edge bar 110 serves to electrically couple the first plurality of cross bars, while the second edge bar 120 serves to electrically couple the second plurality of cross bars 122.
The side-edge cross bars 114 at the extreme edges of the wafer 100 are consistent with the intermediate cross bars 112. In particular, the width and thickness of the side-edge cross bars 114 is the same as that of the intermediate cross bars 112. The length of the side-edge cross bars 114 may be equal to or less than that of the intermediate cross bars 112 depending on whether the silicon wafer has been trimmed in the shape of a square or other polygon, for example. The gap between each of the p-type intermediate cross bars 112 and an adjacent n-type cross bar 122 is the same as the gap between each of side-edge cross bars 114 and an adjacent n-type cross bar.
Photons of sufficient energy incident on the wafer 100 generally generate electron-hole pairs. The ejected electrons are drawn to the p-type semiconductor and collected by the cross bars 112, 114, and the holes drawn to the n-type semiconductor and collected by the cross bars 122. Do to placement of an intermediate cross bar 112 between two adjacent n-type cross bars 122, the upper half of each intermediate cross bar 112 collects electrons from the region bounded by the first of the two adjacent n-type cross bars while the lower half of the of the intermediate cross bar collects holes from the region bounded by the second of the two adjacent n-type cross bars. Thus, the effective collection area of an intermediate cross bar 112 associated with a single p-type cross bar is defined by the region spanning the full length of the cross bar and the distance between two consecutive n-type cross bars 122. The wafer 100 may further include one or more conductive layers of metallization bonded to the p-type and n-type semiconductors to efficiently conduct the current collected by the wafer to electrical contacts coupled to other cells or an electrical load. The conductive layers, including copper and tin, are generally 60 milli-inches (mils) thick.
While solar cells may be formed from substantially whole wafers, some solar panels employ a plurality of smaller silicon dies cut from a wafer to increase its packing density, The dies may then be bonded to a substrate providing structural support and thermal conductivity using solder that forms a bond when heated to its reflow temperature. Solder paste may be applied in select regions to the bonding surface and the combination of die and substrate subjected to a solder reflow oven. Illustrated in FIG. 2 is a plan view of a portion of a photovoltaic die 200 with a plurality of cross bars 112 associated with the p-type semiconductor, a plurality of cross bars associated 122 associated with the n-type conductor, and pre-reflow solder paste for bonding the die to a substrate applied to the cross bars. In this embodiment, the solder paste is applied to the die 200 using a stencil (not shown) having a pattern adapted to apply a plurality of beads of solder paste arrayed along the conductive surfaces of the die 200. Both the first set of solder beads 202 of equal size coinciding with the p-type semiconductor 112 and second set of solder beads 204 of equal size coinciding with the n-type semiconductor 122 are rectangular beads uniformly arrayed between the die 200 to the substrate. The solder paste is generally a bismuth-tin-silver mixture with a melting temperature of approximately 140 degrees Celsius and a reflow temperature of 160 degrees Celsius, although alternative solder pastes may also be used.
The maximum size of a die 200 that may be bonded to a substrate is, however, generally limited due to the deformation of the die when subject to heat. In particular, the heat of the reflow over induces greater curvature in the die 200 than the substrate, which causes the die to peal away from the substrate and form gaps between the die and substrate that degrade or inhibit proper solder bonding there between. Illustrated in FIG. 3 is an edge-on view of the photovoltaic die 200 and substrate 390 when subjected to elevated temperatures. The die 200, including layers of silicon and conductive traces (not shown), is predisposed to bend or curve in the solder reflow process do to the difference in the coefficient of thermal expansion (CTE) between the silicon and underlying conductive layers. As a result, the outer edges of the die 200 separate from and pull above the substrate 390. The distance, d, between the die 200 and substrate 390 generally varies depending on the distance from the center of the chip. The distance is generally smallest at the center of the die 200 and increases toward the periphery of the die where the separation distance 304 is maximal.
The quality of the electrical bonding between the die 200 and substrate 390 may vary significantly depending on the heat-induced curvature of the die 200. Ideally the solder beads should flow together to form a single continuous layer of solder bond. When subjected to the heat of the reflow over, solder beads 310 proximate to the center of the die generally maintain contact between the die 200 and substrate 390 when the solder melting point is reached, thus enabling the solder to effectively bond to both components. Solder beads 312 further away from the center of the die 200 maintain contact between the die 200 and substrate 390 after the solder melting point is reached, but may be unable to flow together with adjacent beads due to the lack of sufficient solder volume to fill the gap between components. Solder beads 314 still further out may fail to bond the die 200 and substrate 390 as a result of the die pulling away from the bead while the reflow oven temperature is above both the solder melting temperature and solidification temperature.
As illustrated in the plan view of the die 200 in FIG. 4, the curvature of the die 200 surface during solder reflow may give to a first region 402 within which there is extensive and uniform electrical bonding between the die 200 and substrate 390. Outside the first region is a second region 404 in which electrical contact between the die 200 and substrate 390 is achieved but the sold bonds form discrete pillars instead of a sheet of uniformly distributed solder. Outside the second region 404 is a third region 406 in which there is little or no solder bonding between the die 200 and substrate 390, thus giving rise to a product defect and lower yields. Note that the boundaries between the regions 402, 404, 406 are generally elliptical due to the elongated character of the cross bars 112, 122. That is, the continuous lengths of metallization of the cross bars 112, 122 produces greater expansion, thus greater curvature, in the horizontal direction while the discontinuous conductive traces in the vertical direction produce less expansion, thus less curvature.
In addition to problems bonding large dies to substrate, the dies cut from wafers generally possess conductive layers of metallization that fail to make the most efficient use of surface area. In particular, a die generally has two side edge cross bars 114 at the extreme edges of the die that have the same width (vertical dimension) as the intermediate cross bars 112. Since the side edge cross bars 114 are adjacent to a single n-type cross bar 122, the side edge cross bars collect electrons from approximately half the area of the intermediate cross bars 112. As such, the width of the side edge cross bars 114 may be unduly large in view of the current collection and thereby degrade the overall collection efficiency of the die 200.
There is therefore a need for a system and method of generating uniform solder bonds wafers or relatively large die and underlying substrate without reducing the production yields. There is also a need for a photovoltaic wafer that minimizes the surface area of the conductive traces and maximizes the overall efficiency of the wafer.